In a digital telecommunications switching system, formatted data packets are transmitted between a variety of locations. One possible originating point for data packets is a microprocessor. Traditionally, the microprocessor has comprised a memory block and a communication controller. A data packet generated by the microprocessor is typically written into a region of the memory block. To conform to industry-standard ATM Adaptation Layer 5 (AAL5) requirements, the packet must be segmented prior to being transmitted to a destination. According to known data packet transmission methods, this segmentation is accomplished by copying segments of the data packet into different regions of the memory block, and combining each segment with an ATM cell header containing destination information for the segment. The individual segments are then transmitted by the communication controller to a destination system, such as an ATM switch, from which the segments are routed to a final destination.
This data packet transmission method involves duplicating the data packet in the memory block, thereby consuming more memory than necessary. Moreover, duplication of data packet segments and triggering of the communication controller to individually transmit the segments uses large amounts of the microprocessor's processing time. Therefore, it is desirable to avoid duplicating the data packet during processing and transmission.